1. Field of the Invention
The present invention relates to a latch-up verification device for layout pattern data of a CMOS semiconductor integrated circuit (IC).
2. Description of the Background Art
FIG. 29 is a cross-sectional view of an inverter serving as a typical gate of a CMOS semiconductor integrated circuit. Referring to FIG. 29, an N.sup.- well region 102 is formed in the upper portion of a P.sup.- substrate 101. P.sup.+ diffusion regions 103, 104 and an N.sup.+ diffusion region 105 are selectively formed in the surface of the N.sup.- well region 102. N.sup.+ diffusion regions 106, 107 and a P.sup.+ diffusion region 108 are selectively formed in the surface of a part of the P.sup.- substrate 101 in which the N.sup.- well region 102 is absent. A gate electrode 109 is formed above intermediate the P.sup.+ diffusion regions 103 and 104 through an oxide film (not shown), and a gate electrode 110 is formed above intermediate the N.sup.+ diffusion regions 106 and 107 through an oxide film (not shown). The gate electrodes 109 and 110 are connected in common.
With the aforesaid arrangement, there is formed a CMOS inverter including a PMOS transistor consisting of the P.sup.+ diffusion regions 103, 104 and the gate electrode 109 and an NMOS transistor consisting of the N.sup.+ diffusion regions 106, 107 and the gate electrode 110. The N.sup.+ diffusion region 105 is provided for securing the potential at the N.sup.- well region 102, and the P.sup.+ diffusion region 108 is provided for securing the potential at the P.sup.- substrate 101.
FIG. 30 is a circuit diagram of a latch-up structure parasitic on a CMOS inverter having the structure of FIG. 29. Referring to FIG. 30, the CMOS inverter as shown in FIG. 29 is provided with a parasitic thyristor formed by a parasitic PNP bipolar transistor T1 consisting of the P.sup.+ diffusion region 104, the N.sup.- well region 102 and the P.sup.- substrate 101 and a parasitic NPN bipolar transistor T2 consisting of the N.sup.+ diffusion region 106, the P.sup.- substrate 101 and the N.sup.- well region 102. Reference character R1 designates a wire resistance between a power supply V.sub.DD and the P.sup.+ diffusion region 104; R2 designates a wire resistance between the power supply V.sub.DD and the N.sup.+ diffusion region 105 or N.sup.- well region 102; R3 designates a wire resistance between the ground level and the P.sup.+ diffusion region 108 or substrate 101; and R4 designates a wire resistance between the ground level and the N.sup.+ diffusion region 106.
In such an arrangement, when a base current flows in the forward direction to either the PNP bipolar transistor T1 or the NPN bipolar transistor T2, a latch-up phenomenon occurs such that both of the PNP and NPN bipolar transistors turn on and enter the positive feedback state to maintain the on-state until the power supply is cut off.
FIG. 31 is a plan view of an exemplary layout pattern in which the latch-up phenomenon occurs. Referring to FIG. 31, reference numeral 111 designates an N.sup.- well region; 112 to 116 designate P.sup.+ diffusion regions; 117 designates an N.sup.+ diffusion region; 119, 120, 122 and 123 designate polysilicon regions; 118, 121 and 135 designate metal wiring regions; 125 designates an N.sup.- well region; 126 and 127 designate P.sup.+ diffusion regions; 128 designates an N.sup.+ diffusion region; 130 designates a polysilicon region; 124, 129, 131 and 139 designates metal wiring regions; 132 to 134 and 147 designate N.sup.+ diffusion regions; 136 and 137 designate N.sup.+ diffusion regions; and 138 and 146 designate P.sup.+ diffusion regions. The crosses of FIG. 31 indicate contact regions. A first power supply voltage V.sub.DD 1 from the power supply V.sub.DD is applied to the metal wiring region 131 through a V.sub.DD wire (not shown), and a second power supply voltage V.sub.DD 2 from the power supply V.sub.DD is applied to the metal wiring region 118 through a V.sub.DD wire (not shown). Input signals S1, S2 and S3 are applied to the polysilicon regions 119, 123 and 130, respectively. The layout pattern is formed on a P substrate (not shown).
FIG. 32 is a circuit diagram showing the electrical connection of the CMOS integrated circuit formed by the layout pattern of FIG. 31. Referring to FIG. 32, a PMOS transistor Q1 includes the P.sup.+ diffusion regions 112, 113 and the polysilicon region 119, and a PMOS transistor Q2 includes the P.sup.+ diffusion regions 113, 114 and the polysilicon region 120.
An NMOS transistor Q3 includes the N.sup.+ diffusion regions 134, 133 and the polysilicon region 119, and an NMOS transistor Q4 includes the N.sup.+ diffusion regions 147, 132 and the polysilicon region 120. A PMOS transistor Q5 includes the P.sup.+ diffusion regions 115, 116 and the polysilicon region 123, and a PMOS transistor Q6 includes the P.sup.+ diffusion regions 126, 127 and the polysilicon region 130. An NMOS transistor Q7 includes the N.sup.+ diffusion regions 136, 137 and the polysilicon region 130.
FIG. 33 is a circuit diagram of a parasitic thyristor structure where attention is focused on the P.sup.+ diffusion region 116 of FIG. 31. The P.sup.+ diffusion region 116, the N.sup.- well region 111 and the P.sup.- substrate form the parasitic PNP bipolar transistor T1. When the PMOS transistor Q6 is on, a potential difference between the power supply voltages V.sub.DD 1 and V.sub.DD 2, if generated, causes a base current to flow in the forward direction to the PNP bipolar transistor T1, resulting in occurrence of latch-up.
FIG. 34 is a plan view of a chip of the CMOSIC. Referring to FIG. 34, cells 141, 142, a V.sub.DD pad 140 and a GND pad 143 are formed on a semiconductor chip 145. Thus the resistance of the wiring path between the V.sub.DD pad 140 and the power supply voltage V.sub.DD 1 at the cell 141 is indicated by R5, and the resistance of the wiring path between the V.sub.DD pad 140 and the power supply voltage V.sub.DD 2 at the cell 142 is indicated by (R5+R6). Likewise, the resistance of the GND wiring path between the GND pad 143 and the ground voltage GND2 at the cell 142 is indicated by R8, and the resistance of the GND wiring path between the GND pad 143 and the ground voltage GND1 at the cell 141 is indicated by (R7+R8).
In general, the conventional CMOSIC has been structured such that a potential difference is generated easily between V.sub.DD 2 and V.sub.DD 1 which should be at the same level due to a difference in resistance based on different V.sub.DD and GND wiring paths, the manner of supply of the power supply voltages to cells, and operating modes and operating timings in the cells.
It will be appreciated from the above description that the layout pattern of the conventional CMOS structure might highly possibly be arranged to generate latch-up easily.
There are many typical layout patterns which easily cause latch-up. The combination of the layout patterns cause latch-up more easily. Therefore it is highly possible to design a layout pattern whose structure causes latch-up easily in designing a CMOS integrated circuit.
It is therefore necessary to verify whether the layout pattern after being designed is liable to cause latch-up. In the conventional verifying method, a person has generally performed a visual verification while being conscious of the regularity of the structure in which latch-up is liable to occur. Such verification, if performed on a large layout pattern, requires much time so that the visual accuracy decreases. As a result, he may overlook the layout pattern in which latch-up is liable to occur. The definition of the layout patterns which easily cause latch-up is somewhat like know-how and is difficult to be grasped quantitatively. In addition, too many items are forbidden when the layout is made. This presents a problem that designers have widely varying verification abilities depending on their experiences.